A reverse-engineering study traces a global-memory load on an Nvidia RTX 4090 from a CUDA vector-add kernel through registers, caches, address translation, interconnects and GDDR6X DRAM. Each 32-thread warp executes an LDG.E instruction that requests four bytes per lane; for contiguous floats, the hardware coalesces those requests into four 32-byte sectors, or one 128-byte cache line. The RTX 4090’s virtually indexed and tagged L1 cache is four-way set-associative and returns hits in about 15.4 ns, or 40 cycles at a locked 2.6 GHz core clock. An L1 miss undergoes virtual-to-physical translation through a per-SM, 16-entry TLB shared across warps. Measurements found TLB misses cost about 4.4 ns, suggesting a larger, fast on-chip translation cache beyond it. Physical requests cross to one of 36 L2 slices, each a 2 MiB, 16-way set-associative cache; L2 hits take about 127 ns. On an L2 miss, one of 12 memory controllers accesses its associated 2 GiB GDDR6X chip. A contiguous 128-byte request requires a DRAM row activation and four column reads. The measured DRAM round trip, including cache and interconnect travel, is about 255 ns or 660 cycles. Other resident warps issue work while a warp waits on the load dependency, helping hide that latency.