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gpu-architectureperformance-optimizationhardware-reverse-engineeringdeveloper-tools

What happens when a GPU reads memory

What happens when a GPU reads memory | Doubleword

blog.doubleword.ai

August 21, 2026

10 min read

🔥🔥🔥🔥🔥

49/100

Summary

A reverse-engineering study traces a global-memory load on an Nvidia RTX 4090 from a CUDA vector-add kernel through registers, caches, address translation, interconnects and GDDR6X DRAM. Each 32-thread warp executes an LDG.E instruction that requests four bytes per lane; for contiguous floats, the hardware coalesces those requests into four 32-byte sectors, or one 128-byte cache line. The RTX 4090’s virtually indexed and tagged L1 cache is four-way set-associative and returns hits in about 15.4 ns, or 40 cycles at a locked 2.6 GHz core clock. An L1 miss undergoes virtual-to-physical translation through a per-SM, 16-entry TLB shared across warps. Measurements found TLB misses cost about 4.4 ns, suggesting a larger, fast on-chip translation cache beyond it. Physical requests cross to one of 36 L2 slices, each a 2 MiB, 16-way set-associative cache; L2 hits take about 127 ns. On an L2 miss, one of 12 memory controllers accesses its associated 2 GiB GDDR6X chip. A contiguous 128-byte request requires a DRAM row activation and four column reads. The measured DRAM round trip, including cache and interconnect travel, is about 255 ns or 660 cycles. Other resident warps issue work while a warp waits on the load dependency, helping hide that latency.

Key Takeaways

  • A contiguous 32-thread RTX 4090 global load of 32-bit values is coalesced into four 32-byte sectors forming one 128-byte cache line.
  • Measured RTX 4090 load-hit latencies were about 15.4 ns for L1 and 127 ns for L2, while a DRAM round trip took about 255 ns.
  • The RTX 4090 has 36 independently serving 2 MiB L2 slices and 12 GDDR6X memory controllers, according to measurements and hardware configuration.
  • The per-SM TLB holds 16 recent translations shared across warps; measured misses take about 4.4 ns.
  • A DRAM miss for the contiguous 128-byte load activates one row and performs four column reads.

What the discussion said

The thread was overwhelmingly about GPU memory architecture as a learning exercise rather than AI itself, so the AI-specific discussion stayed narrow. The one substantive AI tangent asked whether increasingly capable automated kernel tuning changes the old hardware-design tradeoff: instead of exposing every complexity in silicon, vendors might build simpler accelerators and let optimization software discover efficient implementations. That possibility was treated as plausible rather than established, with an explicit concern that dedicated tensor or neural processors can gain simplicity only by becoming too narrow for broader workloads. Several readers also brushed against a practical issue for AI systems work: understanding and tuning modern GPU behavior is difficult when critical implementation details are undocumented. One response suggested that competing hardware documentation could provide a clearer conceptual route than reverse-engineering opaque NVIDIA behavior. But nobody supplied evidence that AI-driven tuning has already made simpler GPU designs broadly successful, nor did the discussion compare model throughput, training costs, or real-world accelerator performance. The dominant mood was technical curiosity: readers appreciated material difficult enough to expose how much they still had to learn, while recognizing that the subject remains inaccessible without deeper computer-architecture grounding.

Where opinion split

Whether AI-based kernel optimization can finally make simpler accelerator hardware viable was the sharpest unresolved point. The optimistic case is that automated tuning can adapt software fast enough to recover performance without ever-more-elaborate hardware; the skeptical caveat is that TPU- and NPU-style simplicity may merely trade flexibility away and limit useful workloads.

Read original article

Community Sentiment

Mixed

Positives

  • AI-assisted kernel tuning could let accelerator designers shift complexity from rigid silicon into software that searches for efficient implementations.

Concerns

  • Dedicated AI accelerators may achieve simplicity by becoming too constrained, leaving them poorly suited to workloads outside their intended neural-network patterns.
  • Opaque GPU memory behavior forces developers toward timing experiments, making serious AI-kernel optimization harder than it should be.

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