Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
divagr.com ·
Qwenputer is an experimental version of Qwen 3.5 4B that embeds a deterministic 32-bit RISC-V CPU in added model weights. The CPU executes during model forward passes, using Qwen’s Gated DeltaNet recurrent-attention state as addressable RAM rather than calling an external tool, sandbox, or runtime. A compiler maps circuit operations onto attention heads, feed-forward units, and DeltaNet memory; generated ADDR, VAL, and STEP tokens form the execution trace. The added core implements RV32IM, the Zba extension, and a small big-number unit across 11 layers added ahead of Qwen’s original 32 layers.
Creator Divyansh Agrawal reports that Qwenputer passes official riscv-tests, matches QEMU program results, and completed 18 million free-running instructions without an error. On reported arithmetic benchmarks, it scored 97.5% to 100%, versus 48.6% to 90% for base Qwen on most listed tests; replaying about 230,000 output positions against a reference machine found zero mismatches. An experimental in-model filesystem stores up to 512 files or roughly 53,000 text tokens in DeltaNet state. The 18.8 GB checkpoint can run on one 24 GB GPU, but requires the RvChat driver and runs calculations in seconds because each CPU instruction consumes several decoded tokens.
What people are saying
Commenters treated the project less as a practical computer than as a striking demonstration of what a model’s internal state can be made to do.
What readers liked
- The fixed-size gated state acting as exact RAM is a compelling alternative to attention caches that balloon with context length, making persistent…
- Embedding a deterministic RISC-V transition system in Qwen turns opaque weights into an unusually concrete computational substrate, and readers…
Concerns raised
- A CPU hidden inside costly LLM inference is computationally perverse for ordinary work; conventional CPUs already deliver the same determinism…
- It remains unclear whether standard optimization can learn this kind of exact circuitry from assembly-like data, or whether it only exists through…
Read full discussion analysis
Source: Hacker News · Based on 15 sampled comments · Analyzed
Discussion overview
Commenters treated the project less as a practical computer than as a striking demonstration of what a model’s internal state can be made to do. The strongest enthusiasm centered on the technical trick: using DeltaNet-style gated state as fixed-size, exact-addressable memory rather than an ever-growing attention cache, then encoding a deterministic RISC-V state machine in weights. That made several readers want to understand neural architectures at a much deeper level, while others connected it to related experiments such as transformer-hosted WASM, tiny networks running Doom, and hand-designed arithmetic circuits.
The thread also pushed past the stunt toward research questions. Readers asked whether a model trained from scratch with this circuitry, or with built-in persistent memory and arithmetic tools, could learn to exploit it during one generation. A more fundamental question was whether ordinary training on enough assembly could discover these weight configurations at all, rather than requiring careful hand construction. Skeptics noted that emulating a CPU inside an expensive neural inference stack does not beat simply using a CPU, and that retraining could erase the delicately embedded machine. Safety references to maliciously steered Qwen were mostly dark humor, but they framed the experiment as deliberately uncanny rather than production-ready.
Points of disagreement
The sharp divide is whether this is merely a costly, cursed emulation trick or a meaningful direction for neural computation. Skeptics argue that conventional hardware already performs deterministic computation directly and cheaply; supporters see the fixed-state memory mechanism and embedded CPU as a valuable probe of what architectures and training could make models reliably do internally.
What readers liked
- The fixed-size gated state acting as exact RAM is a compelling alternative to attention caches that balloon with context length, making persistent model-side state feel less like a metaphor.
- Embedding a deterministic RISC-V transition system in Qwen turns opaque weights into an unusually concrete computational substrate, and readers found that genuinely illuminating.
- The experiment sparked serious interest in models trained with native memory, calculators, and other within-generation tools, rather than bolting capabilities on through multi-turn calls.
- Related hand-built neural computers suggest the idea is not isolated novelty: commenters see a growing design space between learned networks and explicitly programmed machines.
Concerns raised
- A CPU hidden inside costly LLM inference is computationally perverse for ordinary work; conventional CPUs already deliver the same determinism without neural overhead.
- It remains unclear whether standard optimization can learn this kind of exact circuitry from assembly-like data, or whether it only exists through painstaking hard-coding.
- Continued training may overwrite the embedded processor, exposing a clash between stable symbolic machinery and neural networks’ tendency toward catastrophic forgetting.
- Jokes about malicious steering point at an uncomfortable boundary: deterministic internal mechanisms do not make a model’s higher-level behavior aligned or safe.
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divagr.com · Published
Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
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Hacker News · divagr.com