risc-v
Latest stories covering risc-v, with summaries and links to related coverage.
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Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam
news
5 min read
Nvidia is extending CUDA support toward RISC-V CPUs, potentially allowing server-class RISC-V systems to host Nvidia GPU compute workloads. CUDA currently supports x86-64 and AArch64 CPUs. Nvidia requires RISC-V systems to use the RVA23 profile and comply with RISC-V server SoC and platform specifications, which cover baseline reliability, availability, serviceability and security features. Nvidia also requires hardware features beyond those specifications, including vector extensions, PCIe cache coherency and peer-to-peer PCIe communication between devices. PCIe coherency prevents GPU DMA transfers from missing modified CPU-cache data or leaving CPUs with stale cached data after GPU writes. Without it, CUDA software would need explicit cache invalidation handling. Peer-to-peer PCIe support allows device-to-device buffer transfers without routing data through CPU memory. ACPI support was another initial obstacle, but the UEFI Forum added RISC-V ACPI support in 2025, and the ratified RISC-V Boot and Runtime Services specification includes ACPI. Nvidia said it is partnering with SiFive, which plans to demonstrate a CUDA-capable system at Hot Chips; the cited example specifications indicate a high-core-count server processor. Nvidia also described NVLink Fusion, which lets partners integrate Nvidia NVLink IP with custom CPUs or accelerators, including potential RISC-V designs, subject to CUDA requirements and support for frameworks such as DOCA and NCCL.
ESP32-S31
tool
2 min read
ESP32-S31 features a dual-core RISC-V architecture and supports both wireless and wired connectivity. It includes 2.4 GHz Wi-Fi 6, IEEE 802.15.4 for Thread and Zigbee, and Bluetooth 5.4 for LE Audio, Direction Finding, and Bluetooth Mesh 1.1.