Can you reverse engineer an ASIC?
blog.janestreet.com
August 6, 2026
5 min read
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51/100
Summary
A new puzzle challenges participants to reverse engineer a chip layout without additional information about its function. Modern chips are initially created from code using hardware description languages like Verilog, which are then synthesized into a netlist.
Key Takeaways
- The article presents a puzzle involving reverse engineering an ASIC using its layout, which includes metal, routing, and active transistor layers.
- Participants are tasked with recovering a netlist from the layout and determining the circuit's purpose, culminating in finding a specific output string.
- A GDS file serves as the geometric description of the chip, containing all necessary information about the circuit's functionality without any labels.
- A warm-up example is provided to familiarize participants with GDS files and circuit layouts, using a simple binary adder as a reference.
Community Sentiment
Positives
- Getting a logic-gate-level netlist from a GDS is trivial with industry-standard chip design tools — it highlights how accessible modern reverse engineering can be for those in the field.
- Circuit designers use extraction tools daily, emphasizing the practicality and efficiency of reverse-engineering processes in the semiconductor industry.
Concerns
- The original story of reverse engineering a GPU using random inputs is far-fetched and misrepresents the complexities involved in ASIC reverse engineering.
- Commenters overwhelmingly agree that applying random current inputs to modern GPUs is absurd, as they have too much state for such simplistic methods to yield results.
- The claim that one could reverse engineer a GPU by connecting oscilloscopes is met with skepticism, revealing a lack of understanding of the intricacies of digital logic.